table 24 recommended operating conditions (4) (v cc = 1.8 to 5.5 v, v ss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter conditions limits unit min. typ. max. f(cntr 0 ) f(cntr 1 ) timer x and timer y input frequency (duty cycle 50%) 4.5 v cc 5.5v 6.25 mhz 4.0 v cc < 4.5v 2 vcc ? 4mhz 2.0 v cc < 4.0v vcc mhz v cc < 2.0v 5 vcc ? 8mhz f(tclk) timer x, timer y, timer 1, timer 2, timer 3, timer 4 clock input frequency (count source frequency of each timer) 4.5 v cc 5.5v 16 mhz 4.0 v cc < 4.5v 4 vcc ? 8mhz 2.0 v cc < 4.0v 2 vcc mhz v cc < 2.0v 10 vcc ? 16 mhz f( ) system clock frequency (1) 4.5 v cc 5.5v 6.25 mhz 4.0 v cc < 4.5v 4 mhz 2.0 v cc < 4.0v vcc mhz v cc < 2.0v 5 vcc ? 8mhz f(x in ) main clock input frequency (duty cycle 50%) (2)(3) 4.5 v cc 5.5v 1.0 16 mhz 2.0 v cc < 4.5v 1.0 8.0 mhz v cc < 2.0v 1.0 20 vcc ? 32 mhz f(x cin ) sub-clock oscillation frequency (duty cycle 50%) (4)(5) 32.768 80 khz system clock frequency [mhz] 6.25 4.0 2.0 1.0 0 1.8 2.0 4.0 4.5 5.5 [v] power source voltage main clock x in frequency [mhz] 16 8.0 4.0 1.0 0 1.8 2.0 4.5 5.5 [v] power source voltage qzrom version
rev.3.02 apr 10, 2008 page 98 of 131 rej03b0177-0302 38d2 group electrical characteristics note: 1. when the port xc switch bit (bit 4 of address 003b 16 ) of cpu mode register is ?1?, the drivability of p6 2 is different from the above. table 25 electrical characteristics (1) (v cc = 1.8 to 5.5 v, v ss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. v oh ?h? output voltage p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 i oh = ? 2.5ma v cc ? 2.0 v i oh = ? 0.6ma v cc =2.5v v cc ? 1.0 v oh ?h? output voltage p3 0 ? p3 7 , p4 0 ? p4 7 , p5 0 ? p5 7 , p6 0 ? p6 2 (1) i oh = ? 5ma v cc ? 2.0 v i oh = ? 1.25ma v cc ? 0.5 i oh = ? 1.25ma v cc =2.5v v cc ? 1.0 v ol ?l? output voltage p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 i ol =5ma 2.0 v i ol =1.25ma 0.5 i ol =1.25ma v cc =2.5v 1.0 v ol ?l? output voltage p4 0 ? p4 7 , p5 0 , p5 1 , p5 4 ? p5 7 , p6 0 ? p6 1 (1) i ol =10ma 2.0 v i ol =2.5ma 0.5 i ol =2.5ma v cc =2.5v 1.0 v ol ?l? output voltage p3 0 ? p3 7 , p5 2 , p5 3 i ol =15ma 2.0 v i ol =3.0ma v cc =2.5v 0.8 v t+ ? v t ? hysteresis cntr 0 , cntr 1 , int 0 ? int 2 , kw 0 ? kw 7 0.5 v v t+ ? v t ? hysteresis r x d 1 , r x d 2 , s clk1 , s clk2 0.5 v v t+ ? v t ? hysteresis reset v cc = 2.0 v to 5.5 v on reset 0.5 v i ih ?h? input current p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 v i =v cc 5.0 a i ih ?h? input current p3 0 ? p3 7 , p4 0 ? p4 7 , p5 0 ? p5 7 , p6 0 ? p6 2 v i =v cc 5.0 a i ih ?h? input current reset , oscsel v i =v cc 5.0 a i ih ?h? input current x in v i =v cc 4.0 a i il ?l? input current p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 v i =v ss pull-up ?off? ? 5.0 a v cc =5.0v, v i =v ss pull-up ?on? ? 60 ? 120 ? 240 a v cc =3.0v, v i =v ss pull-up ?on? ? 25 ? 50 ? 100 a i il ?l? input current p3 0 ? p3 7 , p4 0 ? p4 7 , p5 0 ? p5 7, p6 0 ? p6 2 v i =v ss pull-up ?off? ? 5.0 a v cc =5.0v, v i =v ss pull-up ?on? ? 30 ? 70 ? 140 a v cc =3.0v, v i =v ss pull-up ?on? ? 6.5 ? 25 ? 45 a i il ?l? input current reset , oscsel v i =v ss ? 5.0 a i il ?l? input current x in v i =v ss ? 4.0 a f(oco) on-chip oscillator frequency v cc =5.0v, ta =25 c 2500 5000 7500 khz qzrom version
rev.3.02 apr 10, 2008 page 99 of 131 rej03b0177-0302 38d2 group a/d converter characteristics note: 1. confirm the recommended operating condition for main clock input frequency. table 26 electrical characteristics (2) (vcc = 1.8 to 5.5 v, v ss = 0 v, ta = ? 20 to 85 c, f(x cin ) = 32.768 khz, output transistors in the cut-off state, a/d converter stopped, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. v ram ram hold voltage when clock is stopped 1.8 5.5 v i cc power source current frequency/2 mode v cc =5.0v f(x in )=12.5mhz 6.4 13 ma f(x in )=12.5mhz (in wit state) 1.5 3.0 ma f(x in )=4mhz 2.2 3.0 ma v cc =2.5v f(x in )=4mhz 0.6 1.2 ma f(x in )=4mhz (in wit state) 0.3 0.6 ma f(x in )=2mhz 0.4 0.8 ma frequency/4 mode v cc =5.0v f(x in )=12.5mhz 3.5 10 ma f(x in )=12.5mhz (in wit state) 1.5 3.0 ma f(x in )=4mhz 1.5 2.5 ma v cc =2.5v f(x in )=8mhz 0.8 2.5 ma f(x in )=8mhz (in wit state) 0.3 0.6 ma f(x in )=4mhz 0.5 1.0 ma frequency/8 mode v cc =5.0v f(x in )=12.5mhz 2.5 5.0 ma f(x in )=12.5mhz (in wit state) 1.5 3.0 ma f(x in )=4mhz 1.2 1.6 ma v cc =2.5v f(x in )=8mhz 0.5 1.0 ma f(x in )=8mhz (in wit state) 0.3 0.6 ma f(x in )=4mhz 0.3 0.6 ma low-speed mode v cc =5.0v f(x in )=stop 17 26 a in wit state 5.5 11 a v cc =2.5v f(x in )=stop 7.0 14 a in wit state 3.5 7.0 a on-chip oscillator mode f(x in ), f(x cin ) = stop v cc =5.0v 270 540 a v cc =2.5v 35 90 a v cc =2.5v (in wit state) 25 75 a all oscillations stopped (in stp state) ta = 2 5 c 0.1 1.0 a ta = 8 5 c 10 a current increased at a/d converter operating f(x in )=12.5 mhz, v cc =5 v in frequency/2, 4 or 8 mode 0.5 ma f(x in )= stop, v cc = 5 v in on-chip oscillator operating 0.5 ma f(x in ) = stop, v cc = 5 v in low-speed mode 0.4 ma table 27 a/d converter recommended operating condition (vcc = 2.0 to 5.5 v, v ss = 0v, ta = ? 20 to 85 c, output transistors in cut-off state, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. v cc power source voltage 2.0 5.0 5.5 v v ih ?h? input voltage adkey 0.9v cc v cc v v il ?l? input voltage adkey 00.7 v cc ? 0.5 v f( ad ) ad converter clock frequency (1) (low-speed ? on-chip oscillator mode excluded) 4.5v < v cc 5.5v 6.25 mhz 4.0v < v cc 4.5v 4.0 mhz 2.0v < v cc 4.0v v cc mhz qzrom version
rev.3.02 apr 10, 2008 page 100 of 131 rej03b0177-0302 38d2 group notes: 1. tc( ad): one cycle of ad conversion clock. ad conversion clock can be selected from source/2 or source/8. source represents the x in input in the frequency/2, 4 or 8 mode and internal on-chip os cillator divided by 4 in the on-chip oscillator mode or the low-speed mode. when the a/d conversion is executed in the frequency/2 mode, frequency/4 mode, or frequency/8 mode, set f(x in ) 500 khz. relationship among ad conversion clock fre quency, power source voltage, ad conve rsion mode and ab solute accuracy. table 28 a/d converter characteristics (vcc = 2.0 to 5.5 v, ta = ? 20 to 85 c, output transistors in cut-off state, low-speed ? on-chip oscillator mode included, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. ? resolution 10 bits abs absolute accuracy (quantification error excluded) 10bitad mode 4.5v < v cc 5.5v, ad conversion clock = f(x in )/2, f(x in )/8 6.25mhz 4lsb 4.0v < v cc 4.5v, ad conversion clock = f(x in )/2, f(x in )/8 4mhz 2.2v v cc 4.0v, ad conversion clock =f(x in )/2, f(x in )/8 vccmhz 2.0v v cc 5.5v, ad conversion clock = f(oco)/8, f(oco)/32 8bitad mode 4.5v < v cc 5.5v, ad conversion clock = f(x in )/2, f(x in )/8 6.25mhz 2 4.0v < v cc 4.5v, ad conversion clock = f(x in )/2, f(x in )/8 4mhz 2.2v < v cc 4.0v, ad conversion clock =f(x in )/2, f(x in )/8 vccmhz 2.0v v cc 2.2v, ad conversion clock = f(x in )/2, f(x in )/8 (6vcc ? 11)mhz 2.0v v cc 2.2v, ad conversion clock = f(x in )/8 vccmhz 2.0v v cc 5.5v, ad conversion clock = f(oco)/8, f(oco)/32 t conv conversion time (1) 10bitad mode tc( ad) 61 tc( ad) 62 s 8bitad mode tc( ad) 49 tc( ad) 50 r ladder ladder resistor 12 35 100 k i vref reference input current v ref =5.0v 50 150 200 a i ia analog input current 5.0 a ad conversion clock frequency [mhz] 6.25 4.0 2.2 2.0 1.0 0 1.8 2.0 2.2 4.0 4.5 5.5 [v] power source voltage v cc note : f(x in ) 500khz f(x in )/2 or f(x in )/8 8bitad=2lsb f(x in )/ 8 8bitad=2lsb f(x in )/2 or f(x in )/8 10bitad=4lsb 8bitad=2lsb ad conversion clock ?frequency/2 mode, frequency/4 and frequency/8 mode: f(x in )/2 or f(x in )/8 10bitad=4lsb 8bitad=2lsb ad conversion clock ?low-speed mode and on-chip oscillator mode: f(oco)/8 or f(oco)/32 (note) qzrom version
rev.3.02 apr 10, 2008 page 101 of 131 rej03b0177-0302 38d2 group lcd power supply characteristics note: 1. the value is the average of each one division resistor. table 29 lcd power supply characteristics ( when connecting division resistors for lcd power supply ) (v cc = 1.8 to 5.5 v, v ss = 0 v, ta = ?20 to 85c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. r lcd division resister for lcd power supply (1) rsel=?10? 200 k rsel=?11? 5 lcd drive timing a lcd circuit division ratio = divided by 1 rsel=?01? 120 rsel=?00? 90 lcd circuit division ratio = divided by 2 rsel=?01? 150 rsel=?00? 120 lcd circuit division ratio = divided by 4 rsel=?01? 170 rsel=?00? 150 lcd circuit division ratio = divided by 8 rsel=?01? 190 rsel=?00? 170 lcd drive timing b lcd circuit division ratio = divided by 1 rsel=?01? 150 rsel=?00? 120 lcd circuit division ratio = divided by 2 rsel=?01? 170 rsel=?00? 150 lcd circuit division ratio = divided by 4 rsel=?01? 190 rsel=?00? 170 lcd circuit division ratio = divided by 8 rsel=?01? 190 rsel=?00? 190 qzrom version
rev.3.02 apr 10, 2008 page 102 of 131 rej03b0177-0302 38d2 group timing requirements and switching characteristics notes: 1. 80 ns in the frequency/2 mode. 2. 32 ns in the frequency/2 mode. 3. when bit 6 of address 001a 16 , 001f 16 are ?1? (clock synchronous). divide this value by four when bit 6 of address 001a 16 , 001f 16 are ?0? (uart). note: 1. when bit 6 of address 001a 16 , 001f 16 are ?1? (clock synchronous). divide this value by four when bit 6 of address 001a 16 , 001f are ?0? (uart). table 30 timing requirements (1) (vcc = 4.0 to 5.5 v, vss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. t w (reset) reset input ?l? pulse width 2 s t c (x in ) main clock input cycle time 4.5v v cc 5.5v (1) 62.5 ns 4.0v v cc < 4.5v 125 ns t wh (x in ) main clock input ?h? pulse width 4.5v v cc 5.5v (2) 25 ns 4.0v v cc < 4.5v 50 ns t wl (x in ) main clock input ?l? pulse width 4.5v v cc 5.5v (2) 25 ns 4.0v v cc < 4.5v 50 ns t c (cntr) cntr 0 , cntr 1 input cycle time 250 ns t wh (cntr) cntr 0 , cntr 1 input ?h? pulse width 105 ns t wl (cntr) cntr 0 , cntr 1 input ?l? pulse width 105 ns t wh (int) int 0 ? int 2 input ?h? pulse width 80 ns t wl (int) int 0 ? int 2 input ?l? pulse width 80 ns t c (s clk ) serial i/o1, 2 clock input cycle time (3) 800 ns t wh (s clk ) serial i/o1, 2 clock input ?h? pulse width (3) 370 ns t wl (s clk ) serial i/o1, 2 clock input ?l? pulse width (3) 370 ns t su (r x d-s clk ) serial i/o1, 2 input setup time 220 ns th(s clk- r x d) serial i/o1, 2 input hold time 100 ns table 31 timing requirements (2) (v cc = 1.8 to 4.0 v, v ss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. t w (reset) reset input ?l? pulse width 2 s t c (x in ) main clock input cycle time (x in input) 2.0v v cc 4.0v 125 ns v cc < 2.0v 166 ns t wh (x in ) main clock input ?h? pulse width 2.0v v cc 4.0v 50 ns v cc < 2.0v 70 ns t wl (x in ) main clock input ?l? pulse width 2.0v v cc 4.0v 50 ns v cc < 2.0v 70 ns t c (cntr) cntr 0 , cntr 1 input cycle time 2.0v v cc 4.0v 1000/ v cc ns v cc < 2.0v 1000/(5 v cc-8) ns t wh (cntr) cntr 0 , cntr 1 input ?h? pulse width tc(cntr)/2-20 ns t wl (cntr) cntr 0 , cntr 1 input ?l? pulse width tc(cntr)/2-20 ns t wh (int) int 0 ? int 2 input ?h? pulse width 230 ns t wl (int) int 0 ? int 2 input ?l? pulse width 230 ns t c (s clk ) serial i/o1, 2 clock input cycle time (1) 2000 ns t wh (s clk ) serial i/o1, 2 clock input ?h? pulse width (1) 950 ns t wl (s clk ) serial i/o1, 2 clock input ?l? pulse width (1) 950 ns t su (r x d-s clk ) serial i/o1, 2 input setup time 400 ns th(s clk- r x d ) serial i/o1, 2 input hold time 200 ns qzrom version
rev.3.02 apr 10, 2008 page 103 of 131 rej03b0177-0302 38d2 group note: 1. the p5 5 /txd 1 [p3 2 /txd 2 ] p-channel output disable bit (bit 4 of address 001b 16 [001f 16 ]) of uart control register is ?0?. note: 1. the p5 5 /txd 1 [p3 2 /txd 2 ] p-channel output disable bit (bit 4 of address 001b 16 [001f 16 ]) of uart control register is ?0?. fig 94. circuit for measuring output switching characteristics table 32 switching characteristics (1) (vcc = 4.0 to 5.5 v, vss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ max. t wh (s clk ) serial i/o1, 2 clock output ?h? pulse width tc(s clk )/2-30 ns t wl (s clk ) serial i/o1, 2 clock output ?l? pulse width tc(s clk )/2-30 ns td(s clk -t x d) serial i/o1, 2 output delay time (1) 140 ns tv(s clk -t x d) serial i/o1, 2 output valid time (1) ? 30 ns tr(s clk ) serial i/o1, 2 clock output rising time 30 ns tf(s clk ) serial i/o1, 2 clock output falling time 30 ns table 33 switching characteristics (2) (v cc = 1.8 to 4.0 v, v ss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ max. t wh (s clk ) serial i/o1, 2 clock output ?h? pulse width tc(s clk )/2-80 ns t wl (s clk ) serial i/o1, 2 clock output ?l? pulse width tc(s clk )/2-80 ns td(s clk -t x d) serial i/o1, 2 output delay time (1) 350 ns tv(s clk -t x d) serial i/o1, 2 output valid time (1) -30 ns tr(s clk ) serial i/o1, 2 clock output rising time 80 ns tf(s clk ) serial i/o1, 2 clock output falling time 80 ns measurement output pin 100pf cmos output measurement output pin 100pf n-channel open-drain output (note) note: when bit 4 of the uart control register (address 001b 16 [address 0ff1 16 ]) is ?1.? (n-channel open-drain output mode) 1k qzrom version
rev.3.02 apr 10, 2008 page 104 of 131 rej03b0177-0302 38d2 group fig 95. timing diagram t c (cntr) t wl (cntr) t wh (cntr) 0.8v cc 0.2v cc cntr 0, cntr 1 int 0 ? int 2 reset t wl (int) t wh (int) 0.8v cc 0.2v cc 0.8v cc 0.2v cc t w (reset) t c (s clk ) t wl (s clk ) 0.8v cc 0.2v cc t wh (s clk ) t f t r t su (r x d-s clk )t h (s clk -r x d) t d (s clk -t x d) t v (s clk -t x d) 0.2v cc 0.8v cc s clk1 s clk2 r x d 1 r x d 2 t x d 1 t x d 2 x in t c (x in ) t wl (x in ) t wh (x in ) 0.8v cc 0.2v cc qzrom version
rev.3.02 apr 10, 2008 page 105 of 131 rej03b0177-0302 38d2 group flash memory version electrical characteristics absolute maximum ratings table 34 absolute maximum ratings symbol parameter conditions ratings unit v cc power source voltage all voltages are based on v ss . when an input voltage is measured, output transistors are cut off. ? 0.3 to 6.5 v v i input voltage p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 7 , p5 0 ? p5 7 , p6 0 ? p6 2 ? 0.3 to v cc + 0.3 v v i input voltage v l1 ? 0.3 to v l2 v v i input voltage v l2 v l1 to v l3 v v i input voltage v l3 v l2 to 6.5 v v i input voltage reset , x in , cnv ss ? 0.3 to v cc + 0.3 v v o output voltage p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 at output port ? 0.3 to v cc + 0.3 v at segment output ? 0.3 to v l3 + 0.3 v v o output voltage com 0 ? com 3 ? 0.3 to v l3 + 0.3 v v o output voltage p3 0 ? p3 7 , p4 0 ? p4 7 , p5 0 ? p5 7 , p6 0 ? p6 2 ? 0.3 to v cc + 0.3 v v o output voltage x out ? 0.3 to v cc + 0.3 v pd power dissipation ta=25 c 300 mw topr operating temperature ?? 20 to 85 c tstg storage temperature - ? 40 to 125 c flash memory version
rev.3.02 apr 10, 2008 page 106 of 131 rej03b0177-0302 38d2 group recommended operating conditions notes: 1. when the a/d converter is used, refer to the recommended operating conditions of the a/d converter. 2. 12.5 mhz < f(x in ) 16 mhz is not available in the frequency/2 mode. table 35 recommended operating conditions (1) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = ? 20 to 85 c unless otherwise noted) symbol parameter limits unit min. typ. max. v cc power source voltage (1) frequency/2 mode (2) f(x in ) 12.5mhz 4.5 5.5 v f(x in ) 8mhz 4.0 5.5 v f(x in ) 4mhz 2.7 5.5 v frequency/4 mode f(x in ) 16mhz 4.5 5.5 v f(x in ) 8mhz 2.7 5.5 v frequency/8 mode f(x in ) 16mhz 4.5 5.5 v f(x in ) 8mhz 2.7 5.5 v low-speed mode 2.7 5.5 v on-chip oscillator mode 2.7 5.5 v v ss power source voltage 0v v l3 lcd power source voltage 2.5 5.5 v v ref a/d converter reference voltage 2.7 v cc v av ss analog power source voltage 0 v v ia analog input voltage an 0 ? an 7 av ss v cc v v ih ?h? input voltage p0 4 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 , p3 0 , p3 2 , p3 5 , p3 6 , p4 0 ? p4 7 , p5 2 , p5 3 , p6 2 0.7v cc v cc v v ih ?h? input voltage p0 0 ? p0 3 , p3 1 , p3 3 , p3 4 , p3 7 , p5 0 , p5 1 , p5 4 ? p5 7 , p6 0 , p6 1 0.8v cc v cc v v ih ?h? input voltage reset 0.8v cc v cc v v ih ?h? input voltage x in 0.8v cc v cc v v il ?l? input voltage p0 4 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 , p3 0 , p3 2 , p3 5 , p3 6 , p4 0 ? p4 7 , p5 2 , p5 3 , p6 2 00.3v cc v v il ?l? input voltage p0 0 ? p0 3 , p3 1 , p3 3 , p3 4 , p3 7 , p5 0 , p5 1 , p5 4 ? p5 7 , p6 0 , p6 1 , cnv ss 00.2v cc v v il ?l? input voltage reset 00.2v cc v v il ?l? input voltage x in 00.2v cc v flash memory version
rev.3.02 apr 10, 2008 page 107 of 131 rej03b0177-0302 38d2 group notes: 1. the total output current is the sum of all the currents fl owing through all the applicable ports. the total average current i s an average value measured over 100 ms. the total peak current is the peak value of all the currents. 2. the peak output current is the peak current flowing in each port. 3. the average output current is average value measured over 100 ms. table 36 recommended operating conditions (3) (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. i oh(peak) ?h? total peak output current (1) p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 , p3 0 ? p3 7 ? 40 ma i oh(peak) ?h? total peak output current (1) p4 0 ? p4 7 , p5 0 ? p5 7 , p6 0 ? p6 2 ? 40 ma i ol(peak) ?l? total peak output current (1) p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 40 ma i ol(peak) ?l? total peak output current (1) p4 0 ? p4 7 , p5 0 , p5 1 , p5 4 ? p5 7 , p6 0 ? p6 2 40 ma i ol(peak) ?l? total peak output current (1) p3 0 ? p3 7 , p5 2 , p5 3 110 ma i oh(avg) ?h? total average output current (1) p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 , p3 0 ? p3 7 ? 20 ma i oh(avg) ?h? total average output current (1) p4 0 ? p4 7 , p5 0 ? p5 7 , p6 0 ? p6 2 ? 20 ma i ol(avg) ?l? total average output current (1) p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 20 ma i ol(avg) ?l? total average output current (1) p4 0 ? p4 7 , p5 0 , p5 1 , p5 4 ? p5 7 , p6 0 ? p6 1 20 ma i ol(avg) ?l? total average output current (1) p3 0 ? p3 7 , p5 2 , p5 3 90 ma i oh(peak) ?h? peak output current (2) p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 ? 2.0 ma i oh(peak) ?h? peak output current (2) p3 0 ? p3 7 , p4 0 ? p4 7 , p5 0 ? p5 7 , p6 2 ? p6 2 ? 5.0 ma i ol(peak) ?l? peak output current (2) p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 5.0 ma i ol(peak) ?l? peak output current (2) p4 0 ? p4 7 , p5 0 , p5 1 , p5 4 ? p5 7 , p6 0 ? p6 2 10 ma i ol(peak) ?l? peak output current (2) p3 0 ? p3 7 , p5 2 , p5 3 30 ma i oh(avg) ?h? average output current (3) p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 ? 1.0 ma i oh(avg) ?h? average output current (3) p3 0 ? p3 7 , p4 0 ? p4 7 , p5 0 ? p5 7 , p6 0 ? p6 2 ? 2.5 ma i ol(avg) ?l? average output current (3) p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 2.5 ma i ol(avg) ?l? average output current (3) p4 0 ? p4 7 , p5 0 , p5 1 , p5 4 ? p5 7 , p6 0 ? p6 2 5.0 ma i ol(avg) ?l? average output current (3) p3 0 ? p3 7 , p5 2 , p5 3 15 ma flash memory version
rev.3.02 apr 10, 2008 page 108 of 131 rej03b0177-0302 38d2 group notes: 1. relationship between system clock frequency and power source voltage is shown in the graph below. 2. when the a/d converter is used, refer to the recommended operating conditions of the a/d converter. 3. 12.5 mhz < f(x in ) 16 mhz is not available in the frequency/2 mode. 4. the oscillation start voltage and the oscillation start time di ffer depending on factors such as the oscillator, circuit cons tants, and operating temperature range. note that oscillation start may be pa rticularly difficult at low voltage when using a high-frequen cy oscillator. 5. when using the microcomputer in low-speed mode, set t he clock input oscillation frequency on condition that f(x cin ) < f(x in )/3.

table 37 recommended operating conditions (4) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = ? 20 to 85 c, unless otherwise noted) symbol parameter conditions limits unit min. typ. max. f(cntr 0 ) f(cntr 1 ) timer x and timer y input frequency (duty cycle 50%) 4.5v v cc 5.5v 6.25 mhz 4.0v v cc < 4.5v 2 vcc ? 4mhz 2.7v v cc < 4.0v vcc mhz f(tclk) timer x, timer y, timer 1, timer 2, timer 3, timer 4 clock input frequency (count source frequency of each timer) 4.5v v cc 5.5v 16 mhz 4.0v v cc < 4.5v 4 vcc ? 8mhz 2.7v v cc < 4.0v 2 vcc mhz f( ) system clock frequency (1) 4.5v v cc 5.5v 6.25 mhz 4.0v v cc < 4.5v 4 mhz 2.7v v cc < 4.0v vcc mhz f(x in ) main clock input frequency (duty cycle 50%) (2)(3) 4.5v v cc 5.5v 1.0 16 mhz 2.7v v cc < 4.5v 1.0 8.0 mhz f(x cin ) sub-clock oscillation frequency (duty cycle 50%) (4)(5) 32.768 80 khz 4.0 4.5 5.5 2.7 4.0 6.25 [mhz] [v] system clock frequency power source voltage 0 2.7 2.7 4.5 5.5 8.0 [mhz] [v] main clock xin frequency power source voltage 0 1.0 16 flash memory version
rev.3.02 apr 10, 2008 page 109 of 131 rej03b0177-0302 38d2 group electrical characteristics note: 1. when the port xc switch bit (bit 4 of address 003b 16 ) of cpu mode register is ?1?, the drivability of p6 2 is different from the above. table 38 electrical characteristics (1) (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. v oh ?h? output voltage p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 i oh = ? 2.5ma v cc ? 2.0 v v oh ?h? output voltage p3 0 ? p3 7 , p4 0 ? p4 7 , p5 0 ? p5 7 , p6 0 ? p6 2 (1) i oh = ? 5ma v cc ? 2.0 v i oh = ? 1.25ma v cc ? 0.5 v v ol ?l? output voltage p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 i ol =5ma 2.0 v i ol =1.25ma 0.5 v ol ?l? output voltage p4 0 ? p4 7 , p5 0 , p5 1 , p5 4 ? p5 7 , p6 0 ? p6 2 (1) i ol =10ma 2.0 v i ol =2.5ma 0.5 v ol ?l? output voltage p3 0 ? p3 7 , p5 2 , p5 3 i ol =15ma 2.0 v v t + ? v t ? hysteresis cntr 0 , cntr 1 , int 0 ? int 2 , kw 0 ? kw 7 0.5 v v t+ ? v t ? hysteresis rxd 1 , rxd 2 , s clk1 , s clk2 0.5 v v t+ ? v t ? hysteresis reset 0.5 v i ih ?h? input current p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 v i =v cc 5.0 a i ih ?h? input current p3 0 ? p3 7 , p4 0 ? p4 7 , p5 0 ? p5 7 , p6 0 ? p6 2 v i =v cc 5.0 a i ih ?h? input current reset , cnv ss v i =v cc 5.0 a i ih ?h? input current x in v i =v cc 4.0 a i il ?l? input current p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 v i =v ss pull-up ?off? ? 5.0 a v cc =5.0v, v i =v ss pull-up ?on? ? 60 ? 120 ? 240 a v cc =3.0v, v i =v ss pull-up ?on? ? 25 ? 50 ? 100 a i il ?l? input current p3 0 ? p3 7 , p4 0 ? p4 7 , p5 0 ? p5 7 , p6 0 ? p6 7 v i =v ss pull-up ?off? ? 5.0 a v cc =5.0v, v i =v ss pull-up ?on? ? 30 ? 70 ? 140 a v cc =3.0v, v i =v ss pull-up ?on? ? 6.5 ? 25 ? 45 a i il ?l? input current reset , cnv ss v i =v ss ? 5.0 a i il ?l? input current x in v i =v ss ? 4.0 a f(oco) on-chip oscillator frequency v cc =5v, ta=25 c 2500 5000 7500 khz flash memory version
rev.3.02 apr 10, 2008 page 110 of 131 rej03b0177-0302 38d2 group a/d converter characteristics note: 1. confirm the recommended operating condition for main clock input frequency. table 39 electrical characteristics (2) (vcc = 2.7 to 5.5 v, v ss = 0 v, ta = ? 20 to 85 c, f(x cin ) = 32.768 khz, output transistors in the cut-off state, a/d converter stopped, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. v ram ram hold voltage when clock is stopped 2.2 5.5 v i cc power source current frequency/2 mode vcc=5.0v f(x in )=12.5mhz 4.0 7.0 ma f(x in )=12.5mhz (in wit state) 2.0 3.5 ma f(x in )=4mhz 2.0 3.5 ma vcc=2.7v f(x in )=4mhz 1.5 3 ma f(x in )=4mhz (in wit state) 1.0 2.5 ma f(x in )=2mhz 1.0 2.5 ma frequency/4 mode vcc=5.0v f(x in )=12.5mhz 3.2 5.6 ma f(x in )=12.5mhz (in wit state) 1.6 3.2 ma f(x in )=4mhz 1.6 3.2 ma vcc=2.7v f(x in )=8mhz 1.6 3.2 ma f(x in )=8mhz (in wit state) 1.0 2.5 ma f(x in )=4mhz 1.0 2.5 ma frequency/8 mode vcc=5.0v f(x in )=12.5mhz 2.5 5 ma f(x in )=12.5mhz (in wit state) 1.5 3 ma f(x in )=4mhz 1.5 3 ma vcc=2.7v f(x in )=8mhz 1.5 3 ma f(x in )=8mhz (in wit state) 1.0 2.5 ma f(x in )=4mhz 1.0 2.5 ma low-speed mode vcc=5.0v f(x in )=stop 400 800 a in wit state ta = 2 5 c 4.0 10 a ta = 8 5 c20 vcc=2.7v f(x in )=stop 300 600 a in wit state ta=25 c3.79 a ta = 8 5 c18 on-chip oscillator mode f(x in ), f(x cin ): stop vcc=5.0v 600 1200 a vcc=2.7v 500 1000 a vcc=2.7v (in wit state) 500 1000 a all oscillations are stopped (in stp state) ta = 2 5 c0.63.0 a ta = 8 5 c1.0 a current increased at a/d converter operating f(x in )=12.5mhz, v cc =5v in frequency/2, 4 or 8 mode 1.0 ma f(x in )=stop, v cc =5v in on-chip oscillator operating 1.0 ma f(x in )=stop, v cc =5v in low-speed mode 0.8 ma table 40 a/d converter recommended operating condition (vcc = 2.7 to 5.5 v, ta = ? 20 to 85 c, output transistors in cut-off state, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. v cc power source voltage 2.7 5.0 5.5 v v ih ?h? input voltage adkey 0.9v cc v cc v v il ?l? input voltage adkey 00.7 v cc ? 0.5 v f( ad ) ad converter clock frequency (1) (low-speed ? on-chip oscillator mode excluded) 4.5v < v cc 5.5v 6.25 mhz 4.0v < v cc 4.5v 4.0 mhz 2.7v < v cc 4.0v v cc mhz flash memory version
rev.3.02 apr 10, 2008 page 111 of 131 rej03b0177-0302 38d2 group notes: 1. tc( ad): one cycle of ad conversion clock. ad conversion clock can be selected from source/2 or source/8. source represents the x in input in the frequency/2, 4 or 8 mode and internal on-chip os cillator divided by 4 in the on-chip oscillator mode or the low-speed mode. when the a/d conversion is executed in the frequency/2 mode, frequency/4 mode, or frequency/8 mode, set f(x in ) 500 khz. relationship among ad conversion clock frequency, power source voltage, ad conversion mode and absolute accuracy. table 41 a/d converter characteristics (vcc = 2.7 to 5.5 v, ta = ? 20 to 85 c, output transistors in cut-off state, low-speed ? on-chip oscillator mode included, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. ? resolution 10 bits abs absolute accuracy (quantification error excluded) 10bitad mode 4.5v < v cc 5.5v, ad conversion clock =f(x in )/2, f(x in )/8 6.25mhz 4lsb 4.0v < v cc 4.5v, ad conversion clock =f(x in )/2, f(x in )/8 4mhz 2.7v v cc 4.0v, ad conversion clock =f(x in )/2, f(x in )/8 vccmhz 2.7v v cc 5.5v, f(oco)/8, f(oco)/32 8bitad mode 4.5v < v cc 5.5v, ad conversion clock =f(x in )/2, f(x in )/8 6.25mhz 2 4.0v < v cc 4.5v, ad conversion clock =f(x in )/2, f(x in )/8 4mhz 2.7v v cc 4.0v, ad conversion clock =f(x in )/2, f(x in )/8 vccmhz 2.7v v cc 5.5v, f(oco)/8, f(oco)/32 t conv conversion time (1) 10bitad mode tc( ad) 61 tc( ad) 62 s 8bitad mode tc( ad) 49 tc( ad) 50 r ladder ladder resistor 12 35 100 k i vref reference input current v ref =5v 50 150 200 a i ia analog input current 5.0 a 4.0 4.5 5.5 4.0 6.25 [mhz] [v] ad conversion clock frequency power source voltage vcc note : f(x in ) 500khz 2.7 2.7 10bitad=4lsb 8bitad=2lsb ad conversion clock ? frequency/2 mode, frequency/4 and frequency/8 mode: f(x in )/2 or f(x in )/8 0 (note) ad conversion clock ? low-speed mode and on-chip oscillator mode: f(oco)/8 or f(oco)/32 f(x in )/2 or f(x in )/8 10bitad=4lsb 8bitad=2lsb flash memory version
rev.3.02 apr 10, 2008 page 112 of 131 rej03b0177-0302 38d2 group lcd power supply characteristics note: 1. the value is the average of each one division resistor. table 42 lcd power supply characteristics ( when connecting division resistors for lcd power supply ) (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ?20 to 85c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. r lcd division resister for lcd power supply (1) rsel=?10? 200 k rsel=?11? 5 lcd drive timing a lcd circuit division ratio = divided by 1 rsel=?01? 120 rsel=?00? 90 lcd circuit division ratio = divided by 2 rsel=?01? 150 rsel=?00? 120 lcd circuit division ratio = divided by 4 rsel=?01? 170 rsel=?00? 150 lcd circuit division ratio = divided by 8 rsel=?01? 190 rsel=?00? 170 lcd drive timing b lcd circuit division ratio = divided by 1 rsel=?01? 150 rsel=?00? 120 lcd circuit division ratio = divided by 2 rsel=?01? 170 rsel=?00? 150 lcd circuit division ratio = divided by 4 rsel=?01? 190 rsel=?00? 170 lcd circuit division ratio = divided by 8 rsel=?01? 190 rsel=?00? 190 flash memory version
rev.3.02 apr 10, 2008 page 113 of 131 rej03b0177-0302 38d2 group timing requirements and switching characteristics notes: 1. 80 ns in the frequency/2 mode. 2. 32 ns in the frequency/2 mode. 3. when bit 6 of address 001a 16 , 001f 16 are ?1? (clock synchronous). divide this value by four when bit 6 of address 001a 16 , 001f 16 are ?0? (uart). note: 1. when bit 6 of address 001a 16 , 001f 16 are ?1? (clock synchronous). divide this value by four when bit 6 of address 001a 16 , 001f 16 are ?0? (uart). table 43 power supply circuit characteristics (vcc = 2.7 to 5.5 v, vss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. td(p-r) internal power source voltage stabilizes time at power-on 2.7 v cc 5.5v 2 ms table 44 timing requirements (1) (vcc = 4.0 to 5.5 v, vss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. t w (reset) reset input ?l? pulse width 2 s t c (x in ) main clock input cycle time 4.5v v cc 5.5v (1) 62.5 ns 4.0v v cc < 4.5v 125 ns t wh (x in ) main clock input ?h? pulse width 4.5v v cc 5.5v (2) 25 ns 4.0v v cc < 4.5v 50 ns t wl (x in ) main clock input ?l? pulse width 4.5v v cc 5.5v (2) 25 ns 4.0v v cc < 4.5v 50 ns t c (cntr) cntr 0 , cntr 1 input cycle time 250 ns t wh (cntr) cntr 0 , cntr 1 input ?h? pulse width 105 ns t wl (cntr) cntr 0 , cntr 1 input ?l? pulse width 105 ns t wh (int) int 0 ? int 2 input ?h? pulse width 80 ns t wl (int) int 0 ? int 2 input ?l? pulse width 80 ns t c (s clk ) serial i/o1, 2 clock input cycle time (3) 800 ns t wh (s clk ) serial i/o1, 2 clock input ?h? pulse width (3) 370 ns t wl (s clk ) serial i/o1, 2 clock input ?l? pulse width (3) 370 ns t su (r x d-s clk ) serial i/o1, 2 input setup time 220 ns t h (s clk -r x d) serial i/o1, 2 input hold time 100 ns table 45 timing requirements (2) (v cc = 2.7 to 4.0 v, v ss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. t w (reset) reset input ?l? pulse width 2 s t c (x in ) main clock input cycle time (x in input) 125 ns t wh (x in ) main clock input ?h? pulse width 50 ns t wl (x in ) main clock input ?l? pulse width 50 ns t c (cntr) cntr 0 , cntr 1 input cycle time 1000/v cc ns t wh (cntr) cntr 0 , cntr 1 input ?h? pulse width tc(cntr)/2 ? 20 ns t wl (cntr) cntr 0 , cntr 1 input ?l? pulse width tc(cntr)/2 ? 20 ns t wh (int) int 0 ? int 2 input ?h? pulse width 230 ns t wl (int) int 0 ? int 2 input ?l? pulse width 230 ns t c (s clk ) serial i/o1, 2 clock input cycle time 2000 ns t wh (s clk ) serial i/o1, 2 clock input ?h? pulse width 950 ns t wl (s clk ) serial i/o1, 2 clock input ?l? pulse width 950 ns t su (r x d-s clk ) serial i/o1, 2 input setup time 400 ns t h (s clk -r x d) serial i/o1, 2 input hold time 200 ns flash memory version
rev.3.02 apr 10, 2008 page 114 of 131 rej03b0177-0302 38d2 group note: 1. the p5 5 /txd 1 [p3 2 /txd 2 ] p-channel output disable bit (bit 4 of address 001b 16 [0ff1 16 ]) of uart control register is ?0?. note: 1. the p5 5 /txd 1 [p3 2 /txd 2 ] p-channel output disable bit (bit 4 of address 001b 16 [0ff1 16 ]) of uart control register is ?0?. fig 96. circuit for measuring output switching characteristics table 46 switching characteristics (1) (vcc = 4.0 to 5.5 v, vss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ max. t wh (s clk ) serial i/o1, 2 clock output ?h? pulse width t c (s clk )/2 ? 30 ns t wl (s clk ) serial i/o1, 2 clock output ?l? pulse width t c (s clk )/2 ? 30 ns t d (s clk -t x d) serial i/o1, 2 output delay time (1) 140 ns t v (s clk -t x d) serial i/o1, 2 output valid time (1) ? 30 ns t r (s clk ) serial i/o1, 2 clock output rising time 30 ns t f (s clk ) serial i/o1, 2 clock output falling time 30 ns table 47 switching characteristics (2) (v cc = 2.7 to 4.0 v, v ss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ max. t wh (s clk ) serial i/o1, 2 clock output ?h? pulse width t c (s clk )/2 ? 80 ns t wl (s clk ) serial i/o1, 2 clock output ?l? pulse width t c (s clk )/2 ? 80 ns t d (s clk -t x d) serial i/o1, 2 output delay time (1) 350 ns t v (s clk -t x d) serial i/o1, 2 output valid time (1) ? 30 ns t r (s clk ) serial i/o1, 2 clock output rising time 80 ns t f (s clk ) serial i/o1, 2 clock output falling time 80 ns measurement output pin 100pf cmos output measurement output pin 100pf n-channel open-drain output (note) 1k note: when bit 4 of the uart control register (address 001b16 [address 0ff116]) is ?1.? (n-channel open-drain output mode) flash memory version
rev.3.02 apr 10, 2008 page 115 of 131 rej03b0177-0302 38d2 group fig 97. timing diagram (in single-chip mode) int 0 ? int 2 cntr 0 , cntr 1 0.2v cc t wl (int) 0.8v cc t wh (int) 0.2v cc 0.2v cc 0.8v cc 0.8v cc 0.2v cc t wl (x in ) 0.8v cc t wh (x in ) t c (x in ) x in 0.2v cc 0.8v cc t w (reset) t f t r 0.2v cc t wl (cntr) 0.8v cc t wh (cntr) t c (cntr) t d (s clk -t x d) t v (s clk -t x d) t c (s clk ) t wl (s clk )t wh (s clk ) t h (s clk -r x d) t su (r x d-s clk ) t x d 1 t x d 2 r x d 1 r x d 2 s clk1 s clk2 reset flash memory version
rev.3.02 apr 10, 2008 page 116 of 131 rej03b0177-0302 38d2 group package outline diagrams showing the latest package dimensions and mounting info rmation are available in the ?packages? section of the renesas technology website. terminal cross section b1 c1 bp c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. * 3 116 17 32 33 48 49 64 f * 1 * 2 x y index mark d h d e h e e b p z d z e detail f c a a 2 a 1 l l 1 previous code jeita package code renesas code plqp0064ga-a 64p6u-a mass[typ.] 0.7g p-lqfp64-14x14-0.80 1.0 0.125 0.35 1.0 1.0 0.20 0.20 0.145 0.09 0.42 0.37 0.32 max nom min dimension in millimeters symbol reference 14.1 14.0 13.9 d 14.1 14.0 13.9 e 1.4 a 2 16.2 16.0 15.8 16.2 16.0 15.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1
rev.3.02 apr 10, 2008 page 117 of 131 rej03b0177-0302 38d2 group terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. index mark * 3 17 32 64 49 116 33 48 f * 1 * 2 x y b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e
rev.3.02 apr 10, 2008 page 118 of 131 rej03b0177-0302 38d2 group appendix note on programming 1. processor status register (1) initialization of the pr ocessor status register it is required to initialize the pr ocessor status register (ps) flags which affect program execution. it is par ticularly essential to initialize the t and d flags because of their effect on calculations. initialize these flags at the beginning of the program. at a reset, the contents of the pr ocessor status register (ps) are undefined except for the i flag which is ?1?. fig. 98 initialization of processor status register flags (2) how to refer the processor status register to refer the contents of the processor status register (ps), execute the php instruction once and then read the contents of (s+1). if necessary, execute the plp instruction to return the stored ps to its original status. fig. 99 stack memory cont ents after php instruction execution 2. decimal calculations (1) instructions for decimal calculations to perform decimal ca lculations, set the de cimal mode (d) flag to ?1? with the sed instruction and execute the adc or sbc instruction. in that case, after the adc or sbc instruction, execute another instruction be fore the sec, clc, or cld instruction. fig. 100 instructions for decimal calculations (2) status flag at decimal calculations when the adc or sbc instructio n is executed in decimal mode (d flag = ?1?), three of the status flags (n, v, and z) are disabled. the carry (c) flag is set to ?1? if a carry is generated and is cleared to ?0? if a borrow is gene rated as a result of a calculation, so it can be used to determine whether the calculation has generated a carry or borrow. initialize the c flag before each calculation. reset initialize the flags main program stored ps (s) (s) + 1 set the decimal mode (d) flag to ?1? execute the adc or sbc instruction nop execute the sec, clc, or cld instruction
rev.3.02 apr 10, 2008 page 119 of 131 rej03b0177-0302 38d2 group 3. jmp instruction when using the jmp instruction (indirect addressing mode), do not specify the address where ?ff 16 ? is allocated to the low- order 8 bits as the operand. 4. multiplication and division instructions (1) the mul and div instructions are not affected by the t and d flags. (2) executing these instructions does not change the contents of the processor status register. 5. read-modify-write instruction do not execute any read-modify-w rite instruction to the read invalid (address) sfr. the read-modify-write instructio n reads 1-byte of data from memory, modifies the data, and wr ites 1-byte the data to the original memory. in the 740 family, the read-modify -write instructions are the following: (1) bit handling instructions: clb, seb (2) shift and rotate instructions: asl, lsr, rol, ror, rrf (3) add and subtract instructions: dec, inc (4) logical operation instruct ions (1?s complement): com although not the read-modify-wr ite instructions, add and subtract/logical oper ation instructions (adc, sbc, and, eor, and ora) when t flag = ?1? operate in the way as the read- modify-write instruction. do not execute them to the read invalid sfr. when the read-modify-write inst ruction is execu ted to the read invalid sfr, the following may result: as reading is invalid, the read value is undefined. the instruction modifies this undefined value an d writes it back, so the written value will be indeterminate. notes on peripheral functions notes on i/o ports 1. use in stand-by state when using the mcu in stand-by state* 1 for low-power consumption, do not leave th e input level of an i/o port undefined. be especially careful to the i/o ports for the n- channel open-drain. in this case, pull-up (connect to vcc) or pull-down (connect to vss) these ports through a resistor. when determining a resistance value, note the following: ? external circuit ? variation in the output level during ordinary operation when using a built-in pull-up resistor, note variations in current values: ? when setting as an input port: fix the input level ? when setting as an output port: prevent current from flowing out externally. even if a port is set to output by the direction register, when the content of the port latc h is ?1?, the transistor becomes the off state, which allows the port to be in the high-impedance state. this may cause the level to be undefined depending on external circuits. as described above, if the input level of an i/o port is left undefined, the power source cu rrent may flow because the potential applied to the input buffe r in the mcu will be unstable. * 1 stand-by state: stop mode by ex ecuting the stp instruction wait mode by executing the wit instruction 2. modifying output data with bit handling instruction when the port latch of an i/o port is modified with the bit handling instruction* 1 , the value of an unspecified bit may change. i/o ports can be set to input mode or output mode in byte units. when the port register is read or written, the following will be operated: ? port as input mode read: read the pin level write: write to the port latch ? port as output mode read: read the port latch or peripheral function output (specifications vary depending on the port) write: write to the port latch (output the content of the port latch from the pin) meanwhile, the bit handling inst ructions are the read-modify- write instructions* 2 . executing the bit handling instruction to the port register allows reading and writing a bit unspecified with the instruction at the same time. if an unspecified bit is set to input mode, the pin level is read and the value is written to the port la tch. at this time, if the original content of the port latch and the pin level do not match, the content of the port latch changes. if an unspecified bit is set to output mode, the port latch is normally read, but the peripheral function output is read in some ports and the value is written to the port latch. at this time, if the original content of the port latch and the peripheral function output do not match, the content of the port latch changes. *1 bit handling instru ctions: clb, seb *2 read-modify-write instructi on: reads 1-byte of data from memory, modifies the data, and writes 1-byte of the data to the original memory.
rev.3.02 apr 10, 2008 page 120 of 131 rej03b0177-0302 38d2 group 3. direction registers the values of the port direction registers cannot be read. this means, it is impossible to use the lda instruction, memory operation instruction when the t flag is ?1?, addressing mode using direction register values as qualifiers, and bit test instructions such as bbc and bbs. it is also impossible to use bit operation instructions such as clb and seb, and read-modify- write instructions to direction registers, including calculations such as ror. to set the direction registers, use instructions such as ldm or sta. 4. pull-up control only for the pin set to input mode, pull-up is controlled by the pull register and the segm ent output disable register. notes on termination of unused pins 1. termination of unused pins perform the following at the shortest possible distance (20 mm or less) from the mcu pins. (1) i/o ports set the ports to input mode and connect each pin to v cc or v ss through a resistor of 1 k to 10 k . an internal pull- up resistor can also be used for the port where the internal pull-up resister is selectable. to set the ports to output mode, leave open at ?l? or ?h? output. ? when setting the ports to ou tput mode and leave open, input mode in the initial state remains until the mode of the ports are switched to output mode by a program after a reset. this may cause the voltage level of the pins to be undefined and the power sour ce current to increase while the ports remains in input mode. for any effects on the system, careful system evaluations should be implemented on the user side. ? the direction registers may be changed due to a program runaway or noise, so reset the registers periodically by a program to increase the program reliability. 2. termination concerns (1) when setting i/o ports to input mode [1] do not leave open ? the power source current may increase depending on the first-stage circuit. ? the ports are more likely affected by noise when compared with the termination shown on the above ?1. (1) i/o ports? [2] do not connect to v cc or v ss directly if the direction registers are ch anged to output mode due to a program runaway or noise, a short circuit may occur. [3] do not connect multiple ports in a lump to v cc or v ss through a resistor. if the direction registers are ch anged to output mode due to a program runaway or noise, a shor t circuit may occur between the ports.
rev.3.02 apr 10, 2008 page 121 of 131 rej03b0177-0302 38d2 group notes on interrupts 1. changing related register settings if the interrupt occurrence sy nchronized with the following settings is not re quired, take the se quence shown below. ? when selecting the external interrupt active edge ? when selecting the interrupt s ource of the interrupt vector address where two or more in terrupt sources are allocated fig. 101 sequence for setting related register in the following cases, the in terrupt request bit of the corresponding interrupt may be set to ?1?. ?int 0 interrupt edge selection bit (bit 0 of interrupt edge se lection register (address 003a 16 )) ?int 1 interrupt edge selection bit (bit 1 of interrupt edge selection register) ?int 2 interrupt edge selection bit (bit 2 of interrupt edge selection register) ?cntr 0 active edge switch bits (bits 6 and 7 of timer x c ontrol register 1 (address 002e 16 )) ?cntr 1 active edge switch bit (bits 6 of timer y mode register (address 0038 16 )) ? int2/key input in terrupt switch bit (bit 3 of interrupt edge selection register) ? timer y/cntr 1 interrupt switch bit (bit 4 of interrupt edge selection register) 2. checking interrupt request bit to check the interrupt request bit with the bbc or bbs instruction immediately after this bit is set to ?0?, take the following sequence. if the bbc or bbs instruction is executed immediately after the interrupt request bit is set to ?0?, the bit value before being set to ?0? is read. fig. 102 sequence for setting interrupt request bit 3. setting unus ed interrupts set the interrupt enable bit of the unused interrupt to ?0? (disabled). set the interrupt edge selection bit (active edge switch bit) or interrupt (source) selection bit. nop (one or more instructions) set the corresponding interrupt enable bit to ?0? (disabled). set the corresponding interrupt request bit to ?0? (no interrupt request). set the corresponding interrupt enable bit to ?1? (enabled). nop (one or more instructions) set the interrupt request bit to ?0? (no interrupt) execute the bbc or bbs instruction
rev.3.02 apr 10, 2008 page 122 of 131 rej03b0177-0302 38d2 group notes on timers 1. frequency divider all timers shares one circuit for the frequency divider to generate the count source. thus the frequency divider is not initialized when each individual timer is activated. when the frequency divider is selected as the count source, a one-cycle delay of the maximum count source will result between wh en the timer is activated and when it starts counting or outputs the waveform. the count source cannot be observed externally. 2. division ratio for timer 1 to 4 the division ratio is 1/(n+1) when the value n (0 to 255) is written to the timer latch. 3. switching frequency and count source for timer 1 to 4, x, and y switch the frequency division or count source* while the timer count is stopped. *this also applies when the frequency divider output is selected as the timer count source and th e count source is switched in conjunction with a transition between operating modes (on- chip oscillator mode, x in mode, or low-speed mode). be careful when changi ng settings in the cp u mode register. 4. setting timer 1 and 2 when stp instruction executed before executing the stp instruction, first set the wait time at return. 5. setting order to timer 1 to 4 when switching the count source of timer 1 to timer 4, a narrow pulse may be generated at the c ount input, which ca uses the timer count value to be undefined. also, if the timers are used in cascade connection, a narrow pul se may be generated at the output when writing to the pervi ous timer, which causes the next timer count value to be undefined. thus set the value from timer 1 in order after setting the count source of timer 1 to timer 4. 6. write to timer 2, 3, and 4 when writing to the latch only, if the write timing to the reload latch and the underflow timing ar e almost the same, the value is set into the timer and the timer latch at the same time. at this time, count is stopped dur ing write operation to the reload latch. 7. timer 3 pwm 0 mode, timer 4 pwm 1 mode (1) when pwm output is suspende d once it starts, the time to resume outputting may be delayed one section (256 ts) of the short interval depending on the level of the output pulse at that time: stop at ?h?: no output delay stop at ?l?: output is delayed time of 256 ts (2) when pwm mode is used, the interrupt requests and values of timer 3 and timer 4 are upda ted every cycle of the long interval (4 256 ts). 8. write order to timer x (1) when timer mode, pulse outpu t mode, event counter mode, or pulse width measurement m ode is set, write to the following registers in the order below: the timer x regi ster (extension) the timer x register (low-order) the timer x regist er (high-order) writing to only one of these registers cannot be performed. when either of the above modes is set and timer x operates as a 16-bit counter, if the timer x register (extension) is never set after a reset release, setting the timer x register (extension) is not required. in that case, write the timer x register (low-order) first and th e timer x register (high-order) next. however, once the timer x register (extension) is written, note that the value is retained in the reload latch. (2) write to the timer x register by the 16-bit unit. do not read the timer x register while write operation is performed. if the write operation is not complete d, normal operation will not be performed. (3) when igbt output mode or pwm mode is set, do not write ?1? to the timer x register (extension). if ?1? has been already written to the timer x register, be sure to write ?0? to the register before use. write to the following registers in the order below: the compare registers 1, 2, 3 (high- and low-order) the timer x regi ster (extension) the timer x register (low-order) the timer x regist er (high-order) the compare registers (high- and low-order) can be written in either order. however, be sure to write both the compare registers 1, 2, 3 and the timer x register at the same time. 9. read order to timer x (1) in all modes, read the follow ing registers in the order below: the timer x register (extension) the timer x register (high-order) the timer x register (low-order) when reading the timer x re gister (extension) is not required, read the timer x regist er (high-order) first and the timer x register (low-order) next. the read order to the compar e registers 1, 2, 3 is not specified. (2) read the timer x register in 16-bit units. do not write to it during read operation. if r ead operation is terminated in progress, normal operation will not be performed.
rev.3.02 apr 10, 2008 page 123 of 131 rej03b0177-0302 38d2 group 10. write to timer x (1) timer x can select either wr iting data to both the latch and the timer at the same time or writing data only by the timer x write control bit (b3) in the timer x mode register (address 002d 16 ). when writing to the latch only, if a value is written to the timer x address, the value is set into the reload latch and the timer is updated at the next underflow. after a reset release, if a value is written to the timer x address, the value is set into the timer and the timer latch at the same time, because they are written simultaneously. when writing to the latch only , if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. at this time, co unt is stopped during write operation to the high-order reload latch. (2) switch the frequency divisi on or count source* while the timer count is stopped. *this also applies when the frequency divider output is selected as the timer count source and th e count source is switched in conjunction with a transition between operating modes (on- chip oscillator mode, x in mode, or low-speed mode). be careful when changi ng settings in the cp u mode register. 11. setting timer x mode register when pwm mode or igbt output mode is set, be sure to set the write control bit in the timer x m ode register to ?1? (writing to latch only). after writing to the t imer x register (high-order), the contents of both registers are simultaneously reflected in the output waveform at the next underflow. 12. timer x output control functions to use the output control functions (int 1 and int 2 ), set the levels of int 1 and int 2 to ?h? for the falling edge active or to ?l? for the rising edge active before switching to igbt output mode. 13. cntr 0 active edge selection (1) setting the cntr 0 active edge switch bits also affects the interrupt active edge at the same time. (2) when the pulse width is measured, set bit 7 of the cntr 0 active edge switch bits to ?0?. 14. when timer x pulse width measurement mode used when timer x pulse mode measurem ent mode is used, enable the event counter wind control data (bit 5 of timer x mode register (address 002d 16 )) by setting to ?0?. if the event counter window control data (bit 5 of timer x mode register (address 002d 16 )) is set to ?1? (disabled) to enable/disable the cntr 0 input, the input is not accepted after the timer 1 underflow. 15. cntr1 active edge selection setting the cntr 1 active edge switch bits also affects the interrupt active edge at the same time. however, in pulse width hl co ntinuous hl measurement mode, the cntr 1 interrupt request is generated at both rising and falling edges of the pin regardless of the settings of the cntr 1 active edge switch bits. 16. read from/write to timer y (1) when reading from/writing to timer y, read from/write to both the high-order and low-or der bytes of timer y. to read the value, read the high-order bytes first and the low-order bytes next. to write the value, write the low-order bytes first and the high-order bytes next. writing/reading sh ould be preformed in 16-bit units. if write/read operation is changed in progress, normal operation will not be performed. (2) timer y can select either writing data to both the latch and the timer at the same time or writing data only by the timer y write control bit (b0) in the timer y control register (address 0039 16 ). when writing to the latch only, if a value is written to the timer y addres s, the value is set into the reload latch and the timer is updated at the next underflow. after a reset release, if a value is written to the timer y address, the value is set into the timer and the timer latch at the same time, because they are written simultaneously. when writing to the latch only , if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. at this time, co unt is stopped during write operation to the high-order reload latch. (3) switch the frequency divisi on or count source* while the timer count is stopped. *this also applies when the frequency divider output is selected as the timer count source and th e count source is switched in conjunction with a transition between operating modes (on- chip oscillator mode, x in mode, or low-speed mode). be careful when changing settings in the cpu mode register. 17. real time port control when switching the setting of the real time port control bits between valid and invalid, write to the timer y mode register in byte units with the ldm or sta in struction so that both bits are switched at the same time. also, before using this function, set the p4 6 and p4 7 port direction registers to output.
rev.3.02 apr 10, 2008 page 124 of 131 rej03b0177-0302 38d2 group notes on serial i/o1 becaouse the operation of the serial i/o2 is as same as serial i/o1, the following notes are written about the serial i/o1. 1. write to baud rate generator write to the baud rate generato r while transmis sion/reception is stopped. 2. setting sequence when serial i/o1 transmit interrupt used to use the serial i/o1 trans mit interrupt, if the interrupt occurrence synchronized with setti ngs is not required, take the following sequence: (1) set the serial i/o1 transmit interrupt enable bit (bit 2 of interrupt control register 2 (address 003f 16 )) to ?0? (disabled). (2) set the transmit enable bit to ?1?. (3) after one or more instructi ons have been executed, set the serial i/o1 transmit interrupt request bit (bit 2 of interrupt request register 2 (address 003d 16 )) to ?0? (no interrupt). (4) set the serial i/o1 transmit interrupt enable bit to ?1? (enabled). when the transmit enable bit is set to ?1?, the transmit buffer empty flag (bit 0 of serial i/o1 status register) and the transmit shift completion flag are set to ?1?. this allows an interrupt reques t to be generated regardless of which interrupt occurrence sour ce has been selected by the transmit interrupt source selection bit (bit 3 of serial i/o1 control register) and the serial i/o1 transmit interrupt request bit is set to ?1?. 3. data transmission control using transmit shift completion flag after transmit data is written to the transmit buffer register, the transmit shift completion flag (bit 2 of serial i/o1 status register (address 0019 16 )) changes from ?1? to ?0? after a delay of 0.5 to 1.5 cycles of the system clock. t hus, after transmit data is written to the transmit buffer register, note this delay when controlling data transmission by referenc ing the transmit shift completion flag. 4. setting serial i/o1 control register before setting the serial i/o1 cont rol register again, first set both the transmit enable bit and the receive enable bit to ?0? and initialize the transmission and reception circuits. fig. 103 sequence of setting serial i/o1 control register 5. pin status after transmission completed after transmission is completed, the txd pin retains the level when transmission is completed. when the internal clock is sel ected in clock synchronous serial i/o mode, the s clk1 pin is set to ?h?. 6. serial i/o1 enable bit during transmit operation during transmission, if the serial i/o1 enable bit (bit 7 of serial i/o1 control register (address 001a 16 )) is set to ?0?, the pin function is set to an i/o port and the internal transmit operation continues even though transmit data is not output externally. also, if the transmit buffer register is written in this state, transmit operation starts internally. if the serial i/o1 enable bit is set to ?1? at this time, transmit data is output to the txd pin from that point. 7. transmission control when external clock selected during data transmission , if the external clock is selected as the synchronous clock, set the transmit enable bit to ?1? while s clk1 is set to ?h?. also, write to th e transmit buffer register while s clk1 is set to ?h?. 8. receive operation in clock synchronous serial i/o mode during reception in clock synchronous serial i/o mode, set both the transmit enable bit and the receive enable bit to ?1?. then write dummy data to the transmit buffer register. when the internal clock is selected as the synchronous clock, the synchronous clock is output at this point and receive operation starts. when the external clock is selected, reception is enabled at this point and inputting the ex ternal clock starts transmit operation. the p5 5 /t x d 1 [p3 2 /txd 2 ] pin outputs dummy data written in the transmit buffer register. 9. transmit/receive operation in clock synchronous serial i/o mode in clock synchronous serial i/o m ode, set the transmit enable bit and the receive enable bit to ?0? simultaneously to stop transmit/receive operations. if on ly one of the operations is stopped, transmission and recep tion cannot be synchronized, which will cause a bit error. set bits 0 to 3, and 6 of the serial i/o1 control register. set both the transmit enable bit (te) and the receive enable bit (re) to ?0? set both the transmit enable bit (te) and the receive enable bit (re), or one of them to ?1?. settings can be made with the ldm instruction at the same time
rev.3.02 apr 10, 2008 page 125 of 131 rej03b0177-0302 38d2 group notes on a/d conversion 1. analog input pin set the signal source impedance fo r analog input low, or equip an analog input pin with an external capacitor of 0.01 f to 1 f. in addition, operations of app lication products s hould be verified thoroughly on the user side. an analog input pin has a built-in capacitor for analog voltage comparison. thus if a signal from the high impedance signal source is input to the analog input pin, charge and discharge noise will be generated. this may cause the a/d conversion/comparison accuracy to drop. 2. clock frequency during a/d conversion the comparator input consists of a capacity coupling. if the conversion rate is too low, the a/d conversion accuracy may deteriorate due to a charge lost, so set f(x in ) 500 khz or more for a/d conversion in x in mode. also, do not execute the stp or wit instruction duri ng a/d conversion. in low-speed mode (when on-chip os cillator is selected), as a/d conversion is performed using th e internal on-chip oscillator, there is no limit on the minimum frequency for f(x in ). 3. adkey function when the adkey enable bit is set to ?1?, the analog input pin selection bits are di sabled. do not execute the a/d conversion by a program while adkey is en abled. enabling adkey does not change bits 0 to 2 of adcon. 4. a/d conversion immediately after adkey function started in the adkey function, a/d conve rsion is not performed to the analog input voltage immediately after starting the function. this causes the a/d conversion resu lt immediately after starting the function to be undefined. if the a/d conversion result of the analog input voltage applied to the adkey pin is required, select the analog input pin correspondi ng to adkey before performing a/d conversion. 5. input voltage applied to adkey pin set the input to the adkey pin into a steep falling waveform and stabilize the input voltage within eight cycles (1 s when f(x in ) = 8 mhz) from the moment the input voltage reaches v il or lower. the actual threshold voltage fo r the adkey pin is between v ih and v il . to prevent unnecessary adkey operation due to noise or other factors, set the adkey pin voltage to v ih (0.9 v cc ) or more while the input is waited. 6. register operation during a/d conversion the a/d conversion operation is not guaranteed if the following are preformed: ? the cpu mode register is operated during a/d conversion operation ? the ad control register is operated during a/d conversion operation ? the stp or wit instructi on is executed during a/d conversion operation 7. a/d converter power source pin connect to the a/d converter power source pin to av ss or v ss whether the a/d conversion function is used or not. if the av ss pin is left open, the mcu may operate incorrectly because the pin will be affect ed by noise or other factors.
rev.3.02 apr 10, 2008 page 126 of 131 rej03b0177-0302 38d2 group notes on lcd drive control circuit 1. setting data to lcd display ram to write data to the lcd display ram when the lcd enable bit is set to ?1? and while lcd is turned on, set fixed data. rewriting with temporary data may cause lcd to flicker. the following shows a processing exam ple to write data to the lcd display ram while lcd is turned on. fig. 104 processing example when writing data to lcd display ram while lcd turned on (1) ccorrect processing lcd on lcd on or off *content at address 0040 16 : ?ff 16 ? off on set lcd display ram data lram0 (address 0040 16 ) ?ff 16 ? lcd on or off? set lcd display ram data lram0 (address 0040 16 ) ?00 16 ? ? set fixed data to lcd display ram (2) incorrect processing lcd on lcd on or off *content at address 0040 16 : ?ff 16 ? off on set lcd display ram data lram0 (address 0040 16 ) ?ff 16 ? lcd on or off? set lcd display ram data lram0 (address 0040 16 ) ?00 16 ? ? set off data to lcd display ram lcd off ? set fixed data to lcd display ram
rev.3.02 apr 10, 2008 page 127 of 131 rej03b0177-0302 38d2 group 2. executing stp instruction execution of the stp instruction sets the lcd enable bit (bit 3 of the lcd mode register) and bits 0 to 5 and bit 7 of the lcd power control register to ?0? and the lcd panel turns off. to make the lcd panel turn on after returning from the stop mode, set these bits to ?1?. 3. v l3 pin to use the lcd drive control circuit while v l3 is set to the voltage equal to v cc , apply the v cc voltage to the v l3 pin and write ?1? to the v l3 connection bit of lcd power control register (address 0038 16 )). 4. lcd drive power supply power supply capacitor may be in sufficient with the division resistance for lcd power supply, and the characteristic of the lcd panel. in this case, there is the method of connecting the bypass capacitor about 0.1 ? 0.33 f to v l1 ? v l3 pins. the example of a strengthening measure of the lcd drive power supply is shown below. fig. 105 strengthening measure example of lcd drive power supply notes on rom correction function 1. returning to main program to return to the main program from the correction program, use the jmp instruction (3-byte instruction). 2. using rom correction function if the rom correction function is used, be sure to enable the rom correction enable bit afte r setting the rom correction register. 3. address do not set addresses other th an the rom area in the rom correction address regi sters. also, do not se t the same address in the rom correction address 1 register and the rom correction address 2 register. 4. rom correction process include the rom correction proc ess in the program beforehand. 5. using no rom correction function if the rom correction function is not used, the rom correction vector can be used as normal ram/rom. when using as normal ram/rom, be sure to set bits 1 and 0 of the rom correction enable register to ?0? (disabled). notes on clock generating circuit 1. oscillation circuit constants the oscillation circui t constants vary depending on the resonator. use values recommended by th e oscillator manufacturer. a feed-back resistor is implemented between the x in and x out pins (an external feed-back resi stor may be required depending on conditions). as no feed-back re sistor is implemented between x cin and x cout , add a feedback resistor of about 10 m . 2. transition between modes when the mcu transits between on-chip oscillator mode, x in mode, or low-speed mode, both the x in and x cin oscillations must be stabilized. be especially careful when turning the power on and returning from stop mode. refer to the clock state transition diagram for a trans ition between each mode. also, set the frequency in the condition that f(x in ) 3 (x cin ). when x in mode is not used (the x in -x out oscillation or external clock input to x in is not performed), connect x in to v cc through a resistor. 3. oscillation stabilization before executing the stp instructio n, set the values * to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch (low-order 8 bits of timer 1 and high-order 8 bits of timer 2). *referential values (set values according to your oscillator and system) ? oscsel = ?l? in the flash memory and qzrom versions: ..................................................................... 0005 16 or more ?oscsel = ?h? in th e qzrom version: .....................................................................01ff 16 or more 4. low-speed mode, x in mode to use low-speed mode or x in mode, wait until oscillation stabilizes after enabling the x in -x out and x cin -x cout oscillation, then switch to the mode. ? connect by the shortest possible wiring. ? connect the bypass capacitor to the v l1 ? v l3 pins as short as possible. (referential value:0.1 ? 0.33 f) v l3 v l2 v l1
rev.3.02 apr 10, 2008 page 128 of 131 rej03b0177-0302 38d2 group notes on flash memory mode ? cpu rewrite mode (1) operating speed during cpu rewrite mode, set the system clock to 4.0 mhz or less using the main clock division ratio selection bits (bits 6 and 7 of address 003b 16 ). (2) prohibited instructions during cpu rewrite mode, the inst ructions which reference data in the flash memory cannot be used. (3) interrupts during cpu rewrite mode, interrupts cannot be used because they reference data in the flash memory. (4) watchdog timer if the watchdog timer has been runni ng already, the internal reset by underflow will not occur because the watchdog timer is continuously cleared during program or erase operation. (5) reset reset is always valid. if cnv ss = ?h? when a reset is released, boot mode is active. the program starts from the address stored in addresses fffc 16 and fffd 16 in boot rom area. notes on watchdog timer 1. watchdog timer underflow the watchdog timer does not ope rate in stop mode, but it continues counting duri ng the wait time to release the stop state and in wait mode. wr ite to the watchdog time r control register so that the watchdog timer will not underflow during these periods. 2. stopping on-chip oscillator oscillation when the on-chip oscillator is selected by the watchdog timer count source selection bit 2, the on-chip oscillator forcibly oscillates and it cannot be stopped. also, in this time, set the stp instruction function selection bit to ?1? at this time. select ?0? ( source) for the watchdog timer count source selection bit 2 at the system wh ich on-chip oscill ator is stopped. 3. watchdog timer control register bits 7 to 5 can be re written only once after a reset. after writing, rewriting is disabled because they are locked. these bits are set to ?0? after a reset. notes on differences between qzrom version and flash memory version the flash memory and qzrom versions differ in their manufacturing processes, built- in rom, memory size, and layout patterns. because of th ese differences, characteristic values, operation margins, noise immunity, and noise radiation and oscillation circuit constants may vary within the specified range of electrical characteristics. when switching to the qzrom version, implement system evaluations equivalent to thos e performed in the flash memory version. confirm page 11 about the differences of functions. notes on power source voltage when the power supply voltage value of the mcu is less than the value indicated in the reco mmended operating conditions, the mcu may not operate normally an d perform unstable operation. in a system where the power source voltage drops slowly when the power source voltage drops or the power is turned off, reset the mcu when the power source voltage is less than the recommended operating conditions , and design the system so that this unstable operation does not cause errors to it. notes on handling power source pins before using the mcu, connect a capacitor suitable for high frequencies as a bypass capacito r between the following: the power source pin (v cc pin) and the gnd pin (v ss pin) the power source pin (v cc pin) and the analog power source input pin (av ss pin). as a bypass capacitor, a ceramic capacitor of 0.01 f to 0.1 f is recommended. also, use the shortest possible wiring to connect a bypass capacitor between the power so urce pin and the gnd pin and between the power source pin a nd the analog power source pin. notes on memory 1. ram the ram content is undefined at a re set. be sure to set the initial value before use.
rev.3.02 apr 10, 2008 page 129 of 131 rej03b0177-0302 38d2 group notes on qzrom version wiring to oscsel pin (1) oscsel = l connect the oscsel pin the s hortest possible to the gnd pattern which is supplied to the v ss pin of the microcomputer. in addition connecting an approximately 5 k resistor in series to the gnd could improve noise immunity. in this case as well as the above mention, connect the pi n the shortest possible to the gnd pattern which is supplied to the v ss pin of the microcomputer. (2) oscsel = h connect the oscsel pin the shortest possible to the v cc pattern which is supplied to the v cc pin of the microcomputer. in addition connecting an approximately 5 k resistor in series to the v cc could improve noise immunity. in this case as well as the above mention, connect the pi n the shortest possible to the v cc pattern which is supplied to the v cc pin of the microcomputer. the oscsel pin is the power source input pin for the built-in qzrom. when programming in the qzrom, the impedance of the oscsel pin is low to allow th e electric current for writing to flow into the built-in qzrom. b ecause of this, noise can enter easily. if noise enters the oscs el pin, abnormal instruction codes or data are read from the qzrom, which may cause a program runaway. fig. 106 wiring for oscsel pin overvoltage in qzrom version make sure that voltage exceeding the v cc pin voltage is not applied to other pins. in particular , ensure that the state indicated by bold lines in figure below does not occur for pin oscsel pin (v pp power source pin for qzrom) during power-on or power- off. otherwise the contents of qzrom could be rewritten. fig. 107 timing diagram (bold-lined periods are applicable) qzrom version product shipped in blank as for the product shipped in blank, renesas does not perform the writing test to user rom area after the assembly process though the qzrom writing test is performed enough before the assembly process. therefore, a writing error of approximate 0.1% may occur. moreover, please note the contac t of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. ordering qzrom writing 1. notes on qzrom writing orders when ordering the qzrom product shipped after writing, submit the mask file (extension: .msk) which is made by the mask file converter mm. ? be sure to set the rom option data* setup when making the mask file by using the mask file converter mm.. the rom code protect is specified acco rding to the rom option data* in the mask file which is submitted at ordering. note that the mask file which has nothing at the rom option data* or has the data other than ?00 16 ?, ?fe 16 ? and ?ff 16 ? can not be accepted. ?set ?ff 16 ? to the rom code protect address in rom data regardless of the presence or ab sence of a protect. when data other than ?ff 16 ? is set, we may ask that the rom data be submitted again. * rom option data: mask option noted in mm 2. data required for qzrom ordering the following are necessary when ordering a qzrom product shipped after writing: ? qzrom writing confirmation form* ? mark specification form* ? rom data: mask file * for the qzrom writing confirmation form and the mark specification form, refer to th e ?renesas technology corp.? homepage (http://www.ren esas.com/homepage.jsp). note that we cannot deal with special font marking (customer's trademark etc.) in qzrom microcomputer. 3. qzrom product receiving procedure when writing to qzrom is performed by user side, the receiving inspection by the fo llowing flow is necessary. oscsel v ss the shortest the shortest about 5 k termination of oscsel pin oscsel v cc the shortest the shortest about 5 k (1) oscsel = l (2) oscsel = h (1) (1) (1) (1) note 1: it shows the microcomputers pin v cc pin voltage oscsel pin voltage ?h? input oscsel pin voltage ?l? input 1.8v 1.8v (1) input voltage to other mcu pins rises before v cc pin voltage. (2) input voltage to other mcu pins falls after v cc pin voltage. note: the internal circuitry is unstable when v cc is below the minimum voltage specification of 1.8 v (shaded portion), so particular care should be exercised regarding overvoltage. (1) (2)
rev.3.02 apr 10, 2008 page 130 of 131 rej03b0177-0302 38d2 group fig. 108 qzrom receiving procedure notes on flash memory version cpu rewrite mode 1. operating speed qzrom product shipped in blank programming verify test receiving inspection of unprotected area (verify test) programming to unprotected area verify test for unprotected area shipping user qzrom product shipped after writing ?protect disabled? ?protect enabled to the protect area 1? renesas receiving inspection (blank check) programming verify test for all area shipping user renesas
rev.3.02 apr 10, 2008 page 131 of 131 rej03b0177-0302 38d2 group during cpu rewrite mode , set the system clock 4.0 mhz or less using the main clock division ratio selection bits (bits 6 and 7 of address 003b 16 ). 2. prohibited instructions the instructions which refer to the internal data of the flash memory cannot be used dur ing the cpu rewrite mode. 3. interrupts the interrupts cannot be used during the cpu rewrite mode because they refer to the internal data of the flash memory. 4. watchdog timer in case of the watchdog timer has been running already, the internal reset generated by watchdog timer underflow does not happen, because of watchdog timer is always clearing during program or erase operation. 5. reset reset is always vali d. in case of cnv ss = ?h? when reset is released, boot mode is active. so the program starts from the address contained in address fffc 16 and fffd 16 in boot rom area. cnv ss pin the cnv ss pin determines the flash memory mode. connect the cnv ss pin the shortest possible to the gnd pattern which is supplied to the v ss pin of the microcomputer. in addition connecting an approximately 5 k . resistor in series to the gnd could improve noise immunity. in this case as well as the above mention, connect the pi n the shortest possible to the gnd pattern which is supplied to the v ss pin of the microcomputer. note. when the boot mode or the stan dard serial i/o mode is used, a switch of the inpu t level to the cnv ss pin is required. fig. 109 wiring for cnv ss pin the shortest cnv ss v ss approx. 5k the shortest (1) (1) note 1: it shows the microcomputers pin.
(1/4) revision history 38d2 group datasheet rev. date description page summary 1.00 jan. 23, 2006 ? first edition issued 2.00 mar. 24, 2006 1 features : description of reset circuit eliminated and power source voltage revised. 3 performance overview: oscillation frequency and power source voltage revised. 4 functional block diagram : description of reset circuit eliminated. 7 fig. 4 and table 3 38d29gc, 38d29g8 added. 12 fig. 9 memory map diagram revised. 15 table 7 non-port function of port p5 4 ? p5 7 revised. related sfrs of port p4 0 and p4 1 revised. 18 fig. 15 (18) port p6 1 revised. 26 fig. 22 timer 12 mode register revised. 29 notes on timer x: (1), (2) revised. 32 ? real time port control revised. 36 fig. 32 uart control register revised. 38 fig. 34 note 1 revised. 42 fig. 38 note 2 revised. 48 fig. 46 memory map revised. 49 note 1 revised. 50 clock output function revised. 51 reset circuit revised. 53 (1)stop mode: description revised. 54 fig. 58 source added. 55 fig. 60 state transitions of system clock: note 3 revised. 56 address of oscillation ouput control register revised. 60 fig. 64 connection of x in and x out revised. 65-75 electrical characteristics added. 2.01 nov. 15, 2006 1 descriotion revised power dissipation described. 3 main clock / sub-clock generating circuits: built-in feed back resistor built-in power dissipation described. 5av ss : gnd input pin analog power source input pin 12 rom and rom code protect address : description revised. fig. 9 is revised. 15 table 7 : as for ckout, non-port function and related sfrs are added. 19 termination of unused pins : as for i/o ports, description added. v l3 : terminations 1 and 2 revised. 25 timer 1, timer 2 : description revised. 28 timer x : description revised. 29 fig. 24 : txcon1 bit 5 = 1 txcon1 bit 5 = 0 31 timer y : description revised. fig. 26 : note added. 37 fig. 33 : note and source added. revision history
(2/4) revision history 38d2 group datasheet 2.01 nov. 15, 2006 42 lcd power circuit ? description added ? fig. 38 : note 3 eliminated ? fig. 39 : bit name described 48 fig. 46 : reserved rom area address revised. rom correction function : description added. 49 fig. 48 : on-chip oscillator on-chip oscillator/4 note added. fig. 49 : on-chip oscillator on-chip oscillator/4 source/1024 count sorce/1024 source/4 count sorce/4 53 (5) low-speed mode : description added 54 fig. 58 : note added and circuit expression is revised. 56 fig. 61 : circuit expression is revised. 57 table 12: as for v ref and av ss , function revised. 59 to 62 fig. 63 to fig. 66 added and revised. 71 table 17 i ih and i il : oscsel added. 75 table 23: note revised. 3.01 sep.18, 2007 ? flash memory version function: added 1 description: flash memory version contents added features: flash memory version contents added power source voltages: flash memory version contents added power dissipation: flash memory version contents added flash memory mode: added 2 fig. 1: note is added 3 table 1: power source voltage: revised and flash memory version contents added power dissipation: flash memory version contents added 5 table 2: led 0 to 7 and kw 0 to 3 are added to pin name 6 pin discription table is divided (to table 2 and table 3) table 3: cnv ss pin is added 7 fig. 3: f (flash memory) is added to memory type 8 flash memory size is added fig. 4: some ?under developing? are erased 9 table 3: flash memory version products are added 10 table 5 ?differences between qzrom and flash memory versions? and ?notes on differences between qzrom and flash memory versions? are added 12 fig. 6: ?push contents of processor status register on stack? position is moved 14 cpu mode register explanation is revised fig. 7: some notes are added 15 fig. 8: flash memory version flow is added 16 fig. 9: flash memory version srf is added 17 fig. 10: flash memory version srf and notes are added 19 table 2: led 0 to 7 and kw 0 to 3 are added to pin name 24-28 ?interrupt? is wholly revised 32 ?frequency divider for timer? is revised 35 ?frequency divider for timer? is revised rev. date description page summary
(3/4) revision history 38d2 group datasheet 3.01 sep.18, 2007 35 ?(6) pulse width measurement mode? is revised 36 ?(3) write to timer x? is revised 37 ?(7) when timer x pulse width measurement mode used? 38 ?(5) real time port control? is added 39 ?notes on timer y? is revised 44 ?conparator and control circuit? is revised 45 fig. 37: revised ?adkey control circuit? is revised 56 ?initial value of watchdog timer? is revised ?bit 6 of watchdog timer control register? and ?? are revised fig. 51: revised fig. 52: revised 57 fig. 54: revised ?[rrf register (rrfr)]? is added 58 explaination is revised fig. 56: revised fig. 57: notes are added 59 fig. 58: revised 60 explanation is revised 62 fig. 61: revised 63 fig. 62: revised 65 table 14: revised 71-88 ?flash memory mode? is added 89 revised to ?notes on use? from ?notes on programming? contents 90 added ?notes on qzrom version? 91 added ?notes on flash memory version? and ?notes on differences between qzrom version an d flash memory version? 94 table 21: revised 95-101 table 22 to 29: ?v ss =0v? are added to condition 95 table 22: v il of x cin is deleted 98 table 25: ?v cc = 4.0 t o 5.0 v? ?v cc = 1.8 to 5.5 v? 100 table 28: ? abs of 10bitad mode ?2.2v < v cc 4.0v? ?2.2v v cc 4.0v? ?1.8v v cc 5.5v? ?2.0v v cc 5.5v ? ? abs of 8bitad mode ?2.2v < v cc 4.0v? ?2.2v v cc 4.0v? ?1.8v v cc 5.5v? ?2.0v v cc 5.5v? ?t conv is separated to 10bitad mode and 8bitadmode, and note is added 102 table 30: t c , t wh , and t wl of x in ?4.5 v to 5.5 v? ?4.5v v cc 5.5v? ?4.0 v to 5.5 v? ?4.0v v cc 5.5v? table 31: t c of x in and cntr, and t wh and t wl of x in ?2.0v < v cc 4.0v? ?2.0v v cc 4.0v? ?v cc 2.0v? ?v cc < 2.0v? 104 fig. 95: x cin timing is deleted 105-115 flash memory version electrical characteristics is added rev. date description page summary
(4/4) revision history 38d2 group datasheet 3.01 sep.18, 2007 118-131 appendix is added 3.02 apr. 09, 2008 2 fig. 1: revised 3 table 1: revised 5 table 2: revised 18 ?direction registers?: peripheral output name is added and deleted 21 fig. 14: revised 23 table 9: revised 25 ?external interrupt pin selection? is deleted 26 fig. 17:revised 29 port name is revised 34 fig. 26: revised 38 ?timer y? is revised 44 fig. 36: revised 49 fig. 41: revised 57 fig. 53 and 54 are revised 58 fig. 56: revised 63 fig. 63: revised 64 fig. 63: revised 65 table 14: revised 66 fig. 65: revised 74 fig. 73: revised 85 fig. 80: revised 86 fig. 81: revised 90 notes on rom code protect is revised 95 table 22: revised 99 table 27: revised 102 table 30: revised 109 note of table 38: revised 110 table 40: revised 129 notes on rom code protect is revised rev. date description page summary
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